1. Field of the Invention
This invention relates to a memory system having a memory device and an error detecting and correcting system installed therein.
2. Description of the Related Art
An electrically rewritable and non-volatile memory device has a feature that the error rate increases as the number of rewrite cycles increases. Specifically, the error rate will be increased more as the integration is improved. Therefore, it is used recently such a technology that an ECC (error correcting code) circuit is installed in a memory chip or a memory controller used for controlling the memory chip (for example, see JP-A-2000-173289).
On the other hand, it is not required of a large capacitive file memory to be a perfectly good product, and there is no problem in practice while there is a sufficiently usable part as a memory area. In this case, it becomes important to be able to avoid certainly bad cell areas. In addition, it becomes necessary to use an ECC circuit, which detects and corrects errors in the memory device. To be able to use a number of data, it is required of the ECC circuit to have such a real time processing rate that is able to prevent the memory device from being delayed in the data transfer.
There has already been proposed an on-chip ECC system, which is configured to generate a warning signal when there are uncorrectable errors in the memory device (for example, see JP-A-2007-305276).